• Analisi
• Arm N1 Neoverse SDP
• Benchmark
• Hypervisor
• Industrial Workload

This thesis evaluates ARM's Coherent Mesh Network (CMN-600), a highly scalable mesh interconnect, which is designed to manage data transfer between compute, accelerators and a wide range of IO devices.
The study uses the N1 sdp infrastructure, a board which implements two CPU clusters, each mounting two "Neoverse N1" cores, that are connected to the CMN-600 among other IO devices.
Software-wise, the evaluation will consider synthetic benchmarks for memory access and IRQ latencies using artificial memory aggressors to emphasize the effects of contention.
These tests are performed both on a Linux installation and on a bare-metal setup, using the Jailhouse hypervisor to do hardware partitioning.
One of the most relevant applications for this infrastructure being in the industrial robotics domain, a realistic application for the board is finally considered.
A pick-and-place workload is implemented with ROS and evaluated in possibly stressed execution environments.

This thesis evaluates ARM's Coherent Mesh Network (CMN-600), a highly scalable mesh interconnect, which is designed to manage data transfer between compute, accelerators and a wide range of IO devices. The study uses the N1 sdp infrastructure, a board which implements two CPU clusters, each mounting two "Neoverse N1" cores, that are connected to the CMN-600 among other IO devices. Software-wise, the evaluation will consider synthetic benchmarks for memory access and IRQ latencies using artificial memory aggressors to emphasize the effects of contention. These tests are performed both on a Linux installation and on a bare-metal setup, using the Jailhouse hypervisor to do hardware partitioning. One of the most relevant applications for this infrastructure being in the industrial robotics domain, a realistic application for the board is finally considered. A pick-and-place workload is implemented with ROS and evaluated in possibly stressed execution environments.