Riassunto analitico
The scaling of MOSFETs down to few nanometer dimensions and the introduction of finFET architectures makes the integration of high-power and low-power components on the same System-on-Chip (SoC) ever more challenging. Low-power fabrication processes are not meant to sustain high power densities. Detrimental effects like hot-carrier injection (HCI) and impact ionization, if not properly mitigated, can cause an early degradation of the device characteristics. In this work a TCAD analysis, design and optimization of an high-voltage LDMOS transistor in finFET technology is presented. The TCAD suite adopted for the simulation is the Sentaurus SDevice suite by Synopsys. LDMOS finFETs with different channel length have been modelled based on realistic layouts, and the doping parameters have been calibrated on experimental data. The impact of numerous variants of the initial design has been assessed for the purpose of device optimization aimed at reducing the detrimental effects of the higher power density and increasing the device cut-off frequency.
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