Riassunto analitico
This thesis proposes an advanced queueing system for heterogeneous computing on embedded devices, implemented using the Vivado Design Suite and the AMD Xilinx Zynq Ultrascale MPSoC ZCU102 board. The designed architecture utilizes an ARM processor to enqueue elements into priority queues, while a MicroBlaze processor manages the resource consumption of the queues based on requests from other MicroBlaze processors. Various types of queues have been explored, including hardware FIFO modules implemented with the AMD Xilinx AXI4-Stream Data FIFO module and software queues located in various memory regions: BRAM (Block RAM), DRAM (Dynamic Random Access Memory), and OCM (On-Chip Memory).
The results highlight the significant effect of the proximity of the MicroBlaze processor on dequeueing time, with BRAM and hardware FIFO queues showing good performance and high predictability. Regarding enqueuing, performance in terms of clock cycles remains consistent across different memory regions, with excellent predictability for BRAM.
Additionally, a queue library executable on Linux has been developed to manage enqueuing and dequeuing operations while maintaining the priority queue structure. This library supports insertion and retrieval of elements with enqueue-side and/or dequeue-side synchronization using the ABQL (Array Based Queuing Locks) mechanism.
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