|Tipo di tesi||Tesi di laurea magistrale|
|Titolo||Modellizzazione e caratterizzazione sperimentale dell'affidabilità di FinFETs|
|Titolo in inglese||Experimental characterization and modeling of FinFETs reliability|
|Struttura||Dipartimento di Ingegneria|
|Corso di studi||Ingegneria Elettronica (D.M.270/04)|
|Data inizio appello||2016-04-14|
|Disponibilità||Accessibile via web (tutti i file della tesi sono accessibili)|
L’integrazione e la velocità di commutazione dei transistor ha visto una crescita esponenziale negli ultimi anni, che ha portato ad una conseguente diminuzione dell’ energia necessaria alla commutazione. Tale miglioramento è stato ottenuto riducendo significativamente la lunghezza di gate dei transistor sotto la guida della Legge di Moore che, durante gli ultimi cinquant’anni, ha previsto l'evoluzione nel tempo della densità di transistor. Tuttavia, negli ultimi anni lo scaling tecnologico ha affrontato numerose sfide e limitazioni a causa dell’imminente raggiungimento dei limiti fisici dell’architettura planare.
Transistors switching speed and integration have seen an exponential growth in the past years, which has consequently decreased switching energy. Such an improvement has been achieved by aggressively reducing the transistor gate length under the guidance of Moore’s Law, which has predicted the evolution of transistor density over time during the last 5 decades. Nevertheless, in the past years scaling has faced several challenges and limitations because physical limits of planar architectures have been almost reached. Among all the possibilities, modifying the geometrical structure of traditional MOSFETs has been an appealing solution in order to keep the pace with Moore’s Law predictions. This caused the introduction on the market of several devices showing non-planar architectures, e.g. FinFETs. Though multi-gate geometries have allowed further technology scaling, the reduction of device dimensions critically enhanced the role of defects and the impact of their stochastic features on the macroscopic device behavior. Actual multi-gate devices are indeed severely affected by stochastic defects-related phenomena like RTN, BTI, and SILC, which constitute severe obstacles for circuit designers. Indeed, these phenomena result in partially stochastic changes of the device behavior over time, especially when the device is under stress conditions. Thus, many efforts have to be focused on the description of defects and the way they affect devices reliability and variability. Understanding defects-related phenomena is hence fundamental to correctly characterize the device behavior. From this perspective, the analysis of the characteristics of such defect-related phenomena may constitute a novel tool to investigate the role of defects and the way they affect device behavior and degradation over time. The purpose of this thesis is to accurately study FinFET degradation during stress. A careful design of experiment (iterative stress/measure approach) has allowed progressively stressing the device under test while monitoring several indicators of the device characteristics. This procedure was applied to a vast number of devices under different conditions (stress voltage, temperature) to yield a statistically significant data set. The cross-correlated analysis of different indicators has allowed devising a consistent picture of the defect-related mechanisms possibly responsible for device degradation. The comparison between experimental results and physics-based simulations performed using MDLab software has allowed gaining specific physical insights into the dynamics of defects generation during stress, revealing significant differences compared to planar technology. The outcomes of this work will be of fundamental importance to improve FinFETs resilience to defects-related phenomena and device degradation.