• Adiabatic Logic
• ECRL
• PAL
• PFAL
• Power consumption

This thesis deals with the power dissipation problem in Very Large Scale Integration (VLSI) designs. Due to the ability to shrink transistor dimensions every few years, power dissipation has raised and now is a main design constrain. Different strategies are available at different level in VLSI design process for optimizing the power consumption, however the reduction of power consumption is every year a major challenge. The main objective of this work is to illustrate some new low power design solutions.
The standard CMOS logic circuit operates charging the load capacitance to the voltage power supply, V_DD, and then discharging it to ground. When the capacitor is discharged to ground, the energy stored, E_C=(C_L V_DD^2)/2 , is transformed into heat and lost. It is possible to reuse this energy, providing it back to the power supply, instead of dissipating it to ground. It is also possible to reduce the power dissipation by charging the load capacitor in a gradual manner. Equations show that charging the capacitor in a gradual manner reduce the amount of dissipated energy as heat if compared with a faster charging method. The Adiabatic Logic uses the two principles cited to reduce the power dissipation. The word “Adiabatic” comes from the Greek and, in thermodynamics, describes a process in which there is no exchange of energy with the environment, eliminating the energy dissipated as heat. Adiabatic Logic also enable the reuse of energy stored in the capacitor, avoiding his discharge to ground. They achieve significant power reduction if compared with the typical CMOS logic design. The main drawbacks of these circuits are: - Complex logic design for execute simple operation – The needs of single/multiple power clocks – Complementary inputs signals – Low speed of operation.
In this work we have analyzed and tested three existing adiabatic logic style: ECRL (Energy Efficient Charge Recovery Logic), PFAL (Positive Feedback Adiabatic Logic) and PAL (Pass-Transistor Adiabatic Logic). The circuits were realized and simulated using Cadence Virtuoso for a 350 nm technology. A comparison of the results is shown and is proved that a significant power reduction is possible if compared with the standard CMOS logic design.

This thesis deals with the power dissipation problem in Very Large Scale Integration (VLSI) designs. Due to the ability to shrink transistor dimensions every few years, power dissipation has raised and now is a main design constrain. Different strategies are available at different level in VLSI design process for optimizing the power consumption, however the reduction of power consumption is every year a major challenge. The main objective of this work is to illustrate some new low power design solutions. The standard CMOS logic circuit operates charging the load capacitance to the voltage power supply, V_DD, and then discharging it to ground. When the capacitor is discharged to ground, the energy stored, E_C=(C_L V_DD^2)/2 , is transformed into heat and lost. It is possible to reuse this energy, providing it back to the power supply, instead of dissipating it to ground. It is also possible to reduce the power dissipation by charging the load capacitor in a gradual manner. Equations show that charging the capacitor in a gradual manner reduce the amount of dissipated energy as heat if compared with a faster charging method. The Adiabatic Logic uses the two principles cited to reduce the power dissipation. The word “Adiabatic” comes from the Greek and, in thermodynamics, describes a process in which there is no exchange of energy with the environment, eliminating the energy dissipated as heat. Adiabatic Logic also enable the reuse of energy stored in the capacitor, avoiding his discharge to ground. They achieve significant power reduction if compared with the typical CMOS logic design. The main drawbacks of these circuits are: - Complex logic design for execute simple operation – The needs of single/multiple power clocks – Complementary inputs signals – Low speed of operation. In this work we have analyzed and tested three existing adiabatic logic style: ECRL (Energy Efficient Charge Recovery Logic), PFAL (Positive Feedback Adiabatic Logic) and PAL (Pass-Transistor Adiabatic Logic). The circuits were realized and simulated using Cadence Virtuoso for a 350 nm technology. A comparison of the results is shown and is proved that a significant power reduction is possible if compared with the standard CMOS logic design.