Riassunto analitico
This document describes the IC design of the receiver of an optical transciver for FM transmission, moving from a discrete design. The design is organized in four phases:
In the initial part of the thesis work, a presentation of the architecture of the receiver is present. In this first phase, there is a theoretical description of the various blocks that make up the receiver, with some mathematical consideration.
After that, the second phase of this work, is focused on the VHDL code implementation of all the blocks that make up the entire chain. Starting from the mathematical expressions or transfer functions that describe the behavior of a given circuit, using the VHDL code, ideal blocks have been created in order to have an ideal model of the receiver, to be used as future reference.
The third chapter is focused on the design at schematic level the receiver previously described in VHDL code. Each block described in VHDL was implemented at the schematic level and tested. At this point the obtained results, the one obtained from the VHDL and the one obtained from the schematic was compared in order to verify the correctness of the schematic.
In the last phase of this document, the work is focused on the design of the layout of the receiver. The aim was to design it with maximum area less than 〖1mm〗^2. Starting from the schematic designed in the previous phase, the procedure was to design the layout block by block, moving from the inner to the top ones. The most important goal was to the design the layout of the receiver as compact as possible. The correctness of the layout was tested by making two important tests: DRC (Design Rule Checking) and the LVS (Layout Versus Schematic).
All the phases, starting from the description of the blocks in VHDL, up to the layout was done by using Cadence software.
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