Riassunto analitico
This thesis deals with the design of an 8-bit Single-Ended SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The whole design is realized in Cadence Suite. This work began by creating the ideal SAR ADC model: each block inside it is implemented in Verilog-A code. This was used throughout the design, as a benchmark to verify the right behavior of the real SAR ADC. The main goal of this thesis is to convert each single block of the ideal SAR ADC model into real, that is formed by real components (MOSFETs, capacitors, resistors, etc.). Each designed block, in the real SAR ADC, must have the same behavior as its corresponding block in the ideal model. The fundamental blocks that are present in the schematic of the designed SAR ADC are: 1) the DACs (Digital-to-Analog Converter) using a switching method that reduces power consumption, during the digitalization, compared to other DACs, 2) the Delay Chain formed of monostables and 3) the Logic Unit which is basically “the mind” of the system and it is entirely implemented by using logic ports. The design was carried out by looking for the best solution, for each block, that minimized the number of used devices (mainly MOSFETs), in order to reduce as much as possible the area required to physically build the entire SAR ADC. Finally, the performance analysis of the designed device was done with the help of appropriate testing blocks realized on Cadence. This analysis allows to measure some Figures-of-Merit (FOM) that quantify ADC dynamic performance.
|
Abstract
This thesis deals with the design of an 8-bit Single-Ended SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The whole design is realized in Cadence Suite. This work began by creating the ideal SAR ADC model: each block inside it is implemented in Verilog-A code. This was used throughout the design, as a benchmark to verify the right behavior of the real SAR ADC. The main goal of this thesis is to convert each single block of the ideal SAR ADC model into real, that is formed by real components (MOSFETs, capacitors, resistors, etc.). Each designed block, in the real SAR ADC, must have the same behavior as its corresponding block in the ideal model. The fundamental blocks that are present in the schematic of the designed SAR ADC are: 1) the DACs (Digital-to-Analog Converter) using a switching method that reduces power consumption, during the digitalization, compared to other DACs, 2) the Delay Chain formed of monostables and 3) the Logic Unit which is basically “the mind” of the system and it is entirely implemented by using logic ports. The design was carried out by looking for the best solution, for each block, that minimized the number of used devices (mainly MOSFETs), in order to reduce as much as possible the area required to physically build the entire SAR ADC. Finally, the performance analysis of the designed device was done with the help of appropriate testing blocks realized on Cadence. This analysis allows to measure some Figures-of-Merit (FOM) that quantify ADC dynamic performance.
|
