Riassunto analitico
During the years, a lot have been done to suppress Short Channel Effects in Silicon MOSFETs. To enhance the control of the gate over the channel, High-K dielectrics have been introduced, and innovative 3D structure realized. However, Silicon is reaching its limits performances when devices are scaled below the 22nm technology node and the interests of researchers is moving from Silicon to high electron mobility materials such as III-V semiconductors.
The objective of this thesis work is to use TCAD as a predictive tool for optimizing new III-V devices, starting from data from laboratory sample and projecting to real manufactured circuits. To do so, we matched the behavior of a real 100nm device realized with III-V materials at MIT Labs (under the guidance of prof. Del Alamo) with TCAD Sentaurus structures. Our effort was mainly devoted to model the Id-Vgs hysteresis, originated in consecutive up-down sweeps, and its correlation with the interface trap density.
In Chapter one, a review of the state-of-the-art in Silicon technology is given, then in chapter two the main characteristic of III-V devices, especially InGaAs, are analyzed. Chapter 3 provides a description of the simulator and of the models activated to match the experimental and the simulated Id-Vgs curves. In Chapter 4 the obtained result are shown and discussed. Chapter 5 concludes this thesis work and contains the summary possible future developments.
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Abstract
During the years, a lot have been done to suppress Short Channel Effects in Silicon MOSFETs. To enhance the control of the gate over the channel, High-K dielectrics have been introduced, and innovative 3D structure realized. However, Silicon is reaching its limits performances when devices are scaled below the 22nm technology node and the interests of researchers is moving from Silicon to high electron mobility materials such as III-V semiconductors.
The objective of this thesis work is to use TCAD as a predictive tool for optimizing new III-V devices, starting from data from laboratory sample and projecting to real manufactured circuits. To do so, we matched the behavior of a real 100nm device realized with III-V materials at MIT Labs (under the guidance of prof. Del Alamo) with TCAD Sentaurus structures. Our effort was mainly devoted to model the Id-Vgs hysteresis, originated in consecutive up-down sweeps, and its correlation with the interface trap density.
In Chapter one, a review of the state-of-the-art in Silicon technology is given, then in chapter two the main characteristic of III-V devices, especially InGaAs, are analyzed. Chapter 3 provides a description of the simulator and of the models activated to match the experimental and the simulated Id-Vgs curves. In Chapter 4 the obtained result are shown and discussed. Chapter 5 concludes this thesis work and contains the summary possible future developments.
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