| Tipo di tesi |
Tesi di laurea magistrale |
| Autore |
TAGLIAVINI, ANDREA
|
| URN |
etd-11252020-163605 |
| Titolo |
Caratterizzazione di applicazioni real-time su ARM CMN-600, uno studio sulla Coherent Mesh Network |
| Titolo in inglese |
CMN-600 characterisation for real-time workloads, a study on ARM's Coherent Mesh Network |
| Struttura |
Dipartimento di Scienze Fisiche, Informatiche e Matematiche |
| Corso di studi |
INFORMATICA (D.M. 270/04) |
| Commissione |
| Nome Commissario |
Qualifica |
| BERTOGNA MARKO |
Primo relatore |
| SOLIERI MARCO |
Secondo relatore |
|
| Parole chiave |
- Analisi
- Arm N1 Neoverse SDP
- Benchmark
- Hypervisor
- Industrial Workload
|
| Data inizio appello |
2020-12-16 |
| Disponibilità |
Accessibile via web (tutti i file della tesi sono accessibili) |
Riassunto analitico
This thesis evaluates ARM's Coherent Mesh Network (CMN-600), a highly scalable mesh interconnect, which is designed to manage data transfer between compute, accelerators and a wide range of IO devices.
The study uses the N1 sdp infrastructure, a board which implements two CPU clusters, each mounting two "Neoverse N1" cores, that are connected to the CMN-600 among other IO devices.
Software-wise, the evaluation will consider synthetic benchmarks for memory access and IRQ latencies using artificial memory aggressors to emphasize the effects of contention.
These tests are performed both on a Linux installation and on a bare-metal setup, using the Jailhouse hypervisor to do hardware partitioning.
One of the most relevant applications for this infrastructure being in the industrial robotics domain, a realistic application for the board is finally considered.
A pick-and-place workload is implemented with ROS and evaluated in possibly stressed execution environments.
|
Abstract
This thesis evaluates ARM's Coherent Mesh Network (CMN-600), a highly scalable mesh interconnect, which is designed to manage data transfer between compute, accelerators and a wide range of IO devices.
The study uses the N1 sdp infrastructure, a board which implements two CPU clusters, each mounting two "Neoverse N1" cores, that are connected to the CMN-600 among other IO devices.
Software-wise, the evaluation will consider synthetic benchmarks for memory access and IRQ latencies using artificial memory aggressors to emphasize the effects of contention.
These tests are performed both on a Linux installation and on a bare-metal setup, using the Jailhouse hypervisor to do hardware partitioning.
One of the most relevant applications for this infrastructure being in the industrial robotics domain, a realistic application for the board is finally considered.
A pick-and-place workload is implemented with ROS and evaluated in possibly stressed execution environments.
|
| File |
|
